Guest Editorial Special Section on Configurable Computing Design-II: Hardware Level Reconfiguration

T HE SECOND issue " Hardware Level Reconfiguration " of the Special Section on Configurable Computing Design deals with hardware level problems: how to build efficient gate arrays; security and fault tolerance issues on configurable hardware ; and implementing floating-point arithmetic and specific decoders on field-programmable gate arrays (FPGAs). The first two papers of this issue deal with gate level problems: with efficient building of reconfigurable logic arrays. The first paper, " A Low-Power Reconfigurable Logic Array Based on Double Gate Transistors, " by P. Beckett, presents a new logic array technology on a gate level. Contrasting with current FPGA structures in which logic and interconnect are built and configured separately, in the new array technology each cell can act as logic or interconnect, or both. This is achieved by using double gate transistors technology. In " Stochastic Physical Synthesis Considering Prerouting Interconnect Uncertainty and Process Variation for FPGAs, " Y. Lin et al. present the in-depth study on stochastic physical synthesis algorithms leveraging statistical static timing analysis for FPGAs. Process variation and prerouting interconnect delay uncertainty affect timing and power for VLSI designs. The sto-chastic clustering, placement, and routing reduce the yield loss. The majority of improvements are achieved during clustering and placement. The paper studies the interaction between each individual design stage and demonstrates that an effective and efficient flow can be developed to use stochastic clustering and deterministic placement and routing. The next three papers deal with fault tolerance management, security, and intrusion detection in reconfigurable computing environment. The first paper of this group, " Applying Dynamic Reconfiguration for Fault Tolerance in Fine-Grained Logic Arrays , " by P. Zipf, deals with the realization of a fault tolerance technique which consists of three parts: fault detection, fault reconfiguration, and fault recovery. All these parts are implemented completely in hardware and form a self-contained system. The technique discussed can be used to exploit dynamic reconfiguration capabilities of programmable arrays to alleviate system vulnerability and thus to enhance their overall reliability. The paper " Reconfigurable Hardware for High-Secu-rity/High-Performance Embedded Systems: The SAFES Perspective, " by G. Guy et al., proposes the security architecture for embedded systems (SAFES). The SAFES architecture is based on three main ideas: 1) reconfigurable security primi-tives; 2) reconfigurable hardware monitors; and 3) a hierarchy of security controllers at the primitive, system, and executive level. This paper stresses that reconfigurable hardware is a real solution to …